A memory is any device associated with a computer that is used to store information, such as programs or data, in digital form. Ever increasingly, newly developed software requires more and more memory in order to run efficiently and smoothly on a computer. It is well-known that one bit defect can ruin the operation of an entire program.
Many types of semiconductor memories, including static random access memories (SRAMs), dynamic random access memories (DRAMs), FIFOs, dual-port memories, and read-only memories of various types, fabricated as individual components and embedded in other integrated circuits such as microprocessors and other logic devices, are containing greater numbers of storage locations, and higher capacity, as the manufacturing technology improves.
For the general commercial market, such a memory is usable only if each and every storage location can be accessed and can store both digital data states. Failure of a single storage location, or bit, thus causes the entire memory (and logic device having an embedded memory) to be non-salable. Considering the relatively large chip size and high manufacturing costs for the high density memories noted hereinabove, such memories are particularly vulnerable to the effect of extremely small (in some cases sub-micron) defects that cause single "stuck" bits.
As a result, many semiconductor memories are now fabricated with redundant storage locations, which are enabled in the event of defects in the primary memory array. For ease of enabling, and also to address row or column defects, the redundant storage locations are generally formed as redundant rows or columns which, when enabled, replace an entire row or column of the primary memory array. The enabling of such redundant storage location is conventionally done during the manufacturing test process, where the primary memory is tested for functionality of the bits therein. The addresses of failing bits are logged, and an algorithm in the automated test equipment determines if the redundant rows or columns available on the circuit are sufficient to replace all of the failing bits. If so, fuses are opened (or, alternatively, anti-fuses may be closed) in the decoding circuitry of the memory so that the failing row or column is no longer enabled by its associated address value, and so that a redundant row or column is enabled by the address associated with the failing row or column.
Especially for high-performance memories, two competing constraints must be dealt with in the design of such redundant storage locations. A first of these constraints is the access time of the redundant storage locations relative to the access time of bits in the primary array. The performance of the computer depends on the speed of operation, which depends upon access times. Access of the redundant elements is typically slower than access of the bits in the primary array (or, at least, slower than the access time of bits in a similar design not utilizing redundancy).
As an example, in U.S. Pat. No. 5,301,153, to implement such redundancy requires the addition of a multiplexer into the critical access path, resulting in the added delay of the multiplexer.
A second constraint in the design of a memory with redundancy is the chip area required to incorporate the redundant elements and associated decode circuitry. The choice of the number of redundant rows and columns generally depends on an estimate of the types of defects which will be encountered in the manufacture of the memories, with the designer required to make a trade-off between the additional chip area required for redundancy and the expected number of otherwise failing circuits which can be repaired by redundancy.
It is therefore an object of this invention to provide a redundancy scheme which allows for efficient repairability without significant decrease in the performance of accesses to the redundant storage locations.